maximum ratings (t a =25c) symbol units drain-source voltage v ds 50 v drain-gate voltage v dg 50 v gate-source voltage v gs 20 v continuous drain current i d 280 ma continuous source current (body diode) i s 280 ma maximum pulsed drain current i dm 1.5 a maximum pulsed source current i sm 1.5 a power dissipation p d 350 mw (note 1) power dissipation p d 300 mw (note 2) power dissipation p d 150 mw (note 3) operating and storage junction temperature t j ,t stg -65 to +150 c thermal resistance ja 357 c/w electrical characteristics per transistor (t a =25c unless otherwise noted) symbol test conditions min max units i gssf v gs =20v, v ds =0v 100 na i gssr v gs =20v, v ds =0v 100 na i dss v ds =50v, v gs =0v 1.0 a i dss v ds =50v, v gs =0v, t j =125c 500 a i d(on) v gs =10v, v ds =10v 500 ma bv dss v gs =0v, i d =10a 50 v CMLDM8002A CMLDM8002Aj surface mount picomini tm dual p-channel enhancement-mode silicon mosfet sot-563 case central semiconductor corp. tm r0 (24-january 2006) description: the central semiconductor CMLDM8002A and CMLDM8002Aj are dual chip enhancement-mode p-channel field effect transistors, manufactured by the p-channel dmos process, designed for high speed pulsed amplifier and driver applications. the CMLDM8002A utilizes the usa pinout configuration, while the CMLDM8002Aj, utilizing the japanese pinout configuration, is available as a special order. these special dual transistor devices offer low r ds(on) and low v ds(on) . notes: (1) ceramic or aluminum core pc board with copper mounting pad area of 4.0 mm 2 (2) fr-4 epoxy pc board with copper mounting pad area of 4.0 mm 2 (3) fr-4 epoxy pc board with copper mounting pad area of 1.4 mm 2 marking code: CMLDM8002A: c08 CMLDM8002Aj: cj8 features: ? dual chip device ? low r ds(on) ? low v ds(on) ? low threshold voltage ? fast switching ? logic level compatible ? small sot-563 package applications: ? load/power switches ? power supply converter circuits ? battery powered portable equipment
central semiconductor corp. tm sot-563 case - mechanical outline CMLDM8002A CMLDM8002Aj surface mount picomini tm dual p-channel enhancement-mode silicon mosfet r0 (24-january 2006) lead code: 1) gate q1 2) source q1 3) drain q2 4) gate q2 5) source q2 6) drain q1 marking code: c08 lead code: 1) source q1 2) gate q1 3) drain q2 4) source q2 5) gate q2 6) drain q1 marking code: cj8 CMLDM8002A (usa pinout) CMLDM8002Aj (japanese pinout) electrical characteristics per transistor - continued (t a =25c unless otherwise noted) symbol test conditions min max units v gs(th) v ds =v gs , i d =250a 1.0 2.5 v v ds(on) v gs =10v, i d =500ma 1.5 v v ds(on) v gs =5.0v, i d =50ma 0.15 v r ds(on) v gs =10v, i d =500ma 2.5 r ds(on) v gs =10v, i d =500ma, t j =125c 4.0 r ds(on) v gs =5.0v, i d =50ma 3.0 r ds(on) v gs =5.0v, i d =50ma, t j =125c 5.0 y fs v ds =10v, i d =200ma 200 msec c rss v ds =25v, v gs =0, f=1.0mhz 7.0 pf c iss v ds =25v, v gs =0, f=1.0mhz 70 pf c oss v ds =25v, v gs =0, f=1.0mhz 15 pf t on v dd =30v, v gs =10v, i d =200ma, 20 ns t off r g =25 , r l =150 20 ns v sd v gs =0v, i s =115ma 1.3 v
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